When initializing a computer system bus, it is typically necessary to allocate various types of resources to devices present on the bus. For instance, the Peripheral Component Interconnect (“PCI”) Bus Standard defines two types of memory address resources that are to be allocated to bus devices upon initialization: the PCI input/output (“I/O”) address space (which might be referred to as “PCI I/O”) and the PCI memory address space (which might be referred to as “PCI memory”).
The PCI memory address space is typically utilized to map memory address resources utilized by a PCI device. For instance, PCI video cards commonly utilize relatively large amounts of the PCI memory address space for storing video information. The PCI I/O address space may be utilized, for instance, to map the internal registers of a bus device into the address space of the host computer. In the PCI Bus Standard each device also has a configuration memory address space utilized for configuring the device.
During platform initialization, PCI bus devices may specify their requirements for memory address resources. The resource requirements specify the type of memory address resources requested (e.g. PCI I/O and/or PCI memory address resources), the amount of memory address resources requested, and an alignment requirement for the requested memory address resources. Each of the PCI devices is then allocated the requested amount of memory address resources if possible. The boundaries of the allocated memory address resources are also aligned according to the alignment requirement specified by each bus device.
The PCI I/O and PCI memory address resources available for allocation to PCI devices is limited and fixed based on a platform build time resource map. As a result, it is possible for the memory address resource requirements of the bus devices installed in a computing system to exceed the available PCI I/O or PCI memory address resources. This is particularly true with respect to multi-processor computing systems. In these systems, multiple central processing units (“CPUs”) can be present (e.g. two, four, or eight), with each of the CPUs having multiple root bridges. As a result, these systems can include many PCI devices, each of which must be allocated PCI I/O and/or PCI memory address resources.
When many PCI devices are present in a computing system, it is possible to exhaust the available PCI I/O or PCI memory address resources before memory address resources have been allocated to all bus devices (this condition might be referred to herein as an “out-of-resource (OOR) condition”). When an OOR condition occurs, bus devices that cannot be allocated PCI I/O or PCI memory address resources will not function and, even more problematic, the computing system can fail to boot.
It is with respect to these and other considerations that the disclosure made herein is presented.